Hi
The ldb clock by default is derived from PLL2 which is at the fixed frequency of 528MHz. Additionally ldb needs a clock which is seven times the pixelclock which limits how close the resulting pixelclock is to the requested one.
You could use a different parent clock which allows to get a closer pixelclock. Assuming you do not use another display output then PLL5 would be a good candidate as with PLL5 the PLL frequency will be set to what you need exactly. To override the parent clock to PLL5 add the following to the &clks device tree node:
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+};
+
Max
P.S. Your question is related to the kernel, so specifying what exact kernel version you use might help.