Hi @sanchayan.tx and @andrecurvello,
I change the clock to 10MHz as suggested and the delays between the words turn to about 50ns. But till this, the problem I have persist. So, with a close look, I see that the time from rise of the CS to the start of the clock positive clock pulse was 20ns. So, I decide to use the variables fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay, to delay the start of the clock and end of the clock from the moments of CS. The result of this was not only the delay in the start and end of the transfer as expected, the sum of the delays appears between each word as well. And now I can read the values correctly.
I set 100ns to fsl,spi-cs-sck-delay and 50ns to fsl,spi-sck-cs-delay.
See the captured images bellow:
