How to do a low-cost carrier board design - Part 2

Thursday, October 13, 2016
Carrier Board

Carrier BoardThe development of a carrier board can be divided into 3 main tasks, system design, schematic capture, and layout. In my previous blog post, I have already talked about the system design and the schematic capturing. Here, I would like to give you some insights to the third phase of the design, the layout. I personally enjoy this phase since it requires a lot of imagination and experience. Also in this part, I would like to focus on designing a low-cost carrier board for a Toradex computer module.


But before we can start with routing the traces, we have to decide what kind of PCB stackup and technology is suitable for our carrier board. As we would like design a low-cost carrier board, we would like to spend some time in optimizing the costs here.

PCB Size: The cost of a PCB increases almost linear with its size. This is another good reason why a computer module can be good for your budget. The small package of the SoC and the high speed DDR3 interface require expensive PCB technology. The size of the PCB with expensive HDI technology is reduced to a module. The big carrier board could be made with cheaper standard technology.

Layer Count: Depending on the complexity of the peripheral schematics, a four maybe even a two-layer board is enough for a carrier board. As the more space you have on your board, the less layers you need. For example, our Evaluation Boards are made with a four-layer PCB while the Ixora required a six-layer board due to its component density.

PCB Thickness: Do you really need a 1.6mm thick PCB? Maybe the rigidness is not needed and a 1mm board is already sufficient. Reducing PCB thickness means reducing material needs. Additionally, if the PCB is thinner, more boards can be stacked during the drilling process which reduced the machine time. Do not underestimate the cost saving by using a thinner PCB. Be aware that the rigidness decreases with the third power of the thickness. Especially if you have large BGA devices on your board, bending the PCB can cause cracks in the solder balls.

Trace Width and Clearance: The PCB costs can be reduced by keeping the trace width and clearance at minimum 150µm (6mil). Trace with and clearance are very often dictated by the package of devices. Maybe it is worth to check for a different package. Trace dimensions below 100µm (4mil) should be avoided since the price will increase massively.

Controlled Impedance: Impedance controlling adds additional cost. Even though it is suggested in our Layout Design Guide to control the impedance of certain signals, there are exceptions in which you can avoid it. The most important factor is the length of the signals on your carrier board. If you have only short traces of e.g. 100Mbit/s Ethernet and USB 2.0 (480 Mbit/s) interfaces, impedance controlling is not really necessary. Also the interface speed needs to be considered. For example, if standard speed (25MHz) for the SD card interface is sufficient, the impedance controlling is not really necessary. There is no golden rule whether impedance controlling is necessary or not. There is a lot of experience involved. If you decide on not controlling the impedance, a clean layout routing is even more important. Try to avoid stubs and consider the current return path of the signals.

Drilling and Milling Tolerances: Do not over specify your design. Tight tolerances increase price. Larger annular rings at vias and THT holes will leave more tolerances to the PCB manufacturer. Adding tear drops will further relax the drilling tolerances and increases the yield. If you use larger drill diameters for your vias, the manufacturer is able to stack more PCBs during the drilling process and the drill bit will last longer.

Surface Finish: Do not underestimate the PCB surface technology costs. The module PCB needs a quite expensive surface finish: electroless nickel immersion gold (ENIG) surface coating with gold plated edge connector pads. This is needed due to the fine pitch BGA devices. You should check whether you can save some money by using hot air solder levelling (HASL) or organic surface protection (OSP) instead. Talk to your PCB manufacturer and your EMS and discuss the surface finish.

Mixing SMD and THT technology: This optimization is related to the assembly cost. If a design features SMD and THT components (e.g. connectors), it should be tried that the SMD components are located only on one side (see the Apalis and Colibri evaluation boards). This allows using cost optimized wave soldering technology. Maybe tenting of the vias is advised. If the board density requires having SMD components on both side (see the Ixora and Iris Board), selective soldering of the THT components is required. Leave at least 5mm space between the THT pads and the SMD components. Otherwise hand soldering cannot be avoided.

After optimizing the cost for the PCB itself, I would like to give you some hints that can help you to have the first version right. First of all, I recommend to read carefully our Layout Design Guide. In this guide, we tried to collect a compressed guideline for avoiding common pitfalls in layout designs, especially with high speed signals. Over the years, I have seen so many layouts which could be easily improved without any additional cost for PCB manufacturing.

I normally start the layout with the signals that I have identified to be the most sensitive ones. Such signals are for example PCIe and similar high speed interfaces. Even though I start with these signals, I am trying to have a concept for routing the lower speed signals as well as the power rails.

I probably do not need to suggest you use the built in design rule check (DRC) of your layout tool carefully. Additionally, I recommend using a second tool to review your production data (Gerber files) independently from the layout tool. In such reviews, I have found already many errors in the settings for creating the Gerber files. It is often worth to ask a colleague to do such a Gerber file review. A useful and free of charge Gerber data viewer is for example the GC-Prevue from GraphiCode.

I hope I have been able to give you some inputs on how you can cost optimize your carrier board. Maybe you have some own strategies for optimizing your hardware design. Please leave a comment and share your experiences.

Author: Peter Lischer, Senior Hardware Development Engineer, Toradex AG
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warren - 6 years 2 months | Reply

A very good article, introduced in great detail

Toradex - 6 years 2 months | Reply

Thank you very much, Warren. We're glad you liked it.

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