How to get DVI working on Colibri Evaluation Board with iMX6

Technical Support
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1

Hi,

I’ve been trying to get the DVI display working on the Colibri Evaluation Board using a Colibri iMX6DL.
the vidargs I use are as follows:

setenv vidargs video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 video=mxcfb1:dev=hdmi,1920x1080M@60,if=RGB24 video=mxcfb2:off fbmem=32M

I have tried many different combinations of vidarg settings (setting mxcfb0, 1 and 2 to hdmi, lcd off and so on) but nothing works.
I have also tried using a DVI to DVI connector, a DVI to HDMI connector and a HDMI adapter board.

The flatflex cable between the colibri and the evaluation board is properly connected.

The linux image I’m using is Toradex’s Colibri-iMX6_LXDE-Image_2.7b2-20170410.

For more info feel free to ask.

Thanks in advance!

2

Hi

Can you provide the output of dmesg and the content of /sys/kernel/debug/clk/clk_summary?
Have a look here.

Note that the i.MX 6 Solo and Dual Lite only have one IPU while the Dual and Quad has two.
So you only have two framebuffers mxcfb0, mxcfb1. Setting something for mxcfb2 on the cmdline will be ignored.

Max

3

Hi Max,

Here is the output of dmesg and clk_summary. I’ve added them in their entirety so not to miss anything. I have also removed mxcfb2:off. I already thought it shouldn’t have been there but was confused because ls /dev/fb* does show fb0, fb1 and fb2.

Meanwhile I’ve been able to get HDMI (only on mxcfb0, mxcfb1 off) working on our own controller board using an HDMI adapter board but on the Colibri Evaluation Board I still don’t get any output on the DVI.

Thanks,
Arnolink text

4

Hi Arno

The clk tree shows, that in fact your primary display output changes the common input clock so that the HDMI pixelclock has a totally wrong frequency of 47.5MHz.

   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 ...
       pll5                               1            1   759999984          0 0  
                      ipu1_di1_pre_sel           1            1    47499999          0 0  
 ...
                                        ipu1_pclk1           1            1    47499999          0 0  
 ...
                      ipu1_di0_pre_sel           1            1    47499999          0 0  
                                        ipu1_pclk0           1            1    23750000          0 0

One could recompile the kernel with a different parent clock for ipu1_di0 so that the two do not influence each other.

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index bfd7681..df12317 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -798,7 +798,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
        }
        /* ipu clock initialization */
-       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
        imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
        imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
        imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);

That way the LCD outupt has to cope with a parent of fixed 540 MHz resulting in a little deviation from the optimum pixelclock which will likely not have any influence.

 ...
       pll5                               1            1  1188000000          0 0  
 ...
                      ipu1_di1_pre_sel           1            1   148500000          0 0  
 ...
                                        ipu1_pclk1           1            1   148500000          0 0  
       pll3                               1            1   480000000          0 0  
                pll3_pfd1_540m            4            4   540000000          0 0  
                   ipu1_di0_pre_sel           1            1   540000000          0 0  
                                     ipu1_pclk0           1            1    25714285          0 0

Max

5

Hi Max,

Thanks for the answer. I’ll check it out.

cheers,
Arno

6

Have you connected an FFC cable between Colibri iMX6 X2 and Colibri Evaluation board X6 connectors?