Setup M4 clock from A5 on VF61

Technical Support
, ,
1

Following the steps in this document I can load a firmware to M4 core and start its execution.
The Rpmsg library on A5 core doesn’t allow to configure M4 core clock and/or bus clock.
When I write a firmware for M4 core and I load and execute it on M4 core through a debugger (for example Keil ULINK-pro) I must set all the clocks through CCM (Clock Controller Module) registers.

How A5 core sets M4 core and bus clocks when it runs WinCE 6?
Which CCM registers can M4 core modify (and how) without falling into HardFault?

After a deeper investigation, I think that the issue I described here is produced by M4 core when it tries to set CCM registers (clock and PLLs).

2

Hi,

Its impossible to tell or the registers we modify as we have algorithms taking care of this automatically. Best is if you tell us what registers you want to write and we can check. You could also use memmap library on WinCE to write clock registers from A5 before running M4.

3

This is the list of registers I set in my M4 firmware:

  • CCM->CCGR4
  • CCM->CCGR3
  • CCM->CCGR2
  • CCM->CCSR to get 396MHz CA5, 396 MHz DDR, 132MHz CM4, and 66MHz bus
  • CCM->CACRR
  • ANADIG->PLL1_CTRL
  • ANADIG->PLL2_CTRL
  • ANADIG->PLL4_CTRL
  • ANADIG->PLL5_CTRL
  • ANADIG->PLL6_CTRL

I suspect the problem is either in one or more of these registers, or in loading the firmware from A5 (LoadAddr 0x3f040000 - ExecuteAddr 0x1F0403A1 - CodeSize 128*1024)

4

I see you are changing a lot of clocks that A5 is using.

CCGR4 OK
CCGR3 OK
CCGR2 OK
CCSR not ok You can change that M4 part from M5 but please do not change this clock ( if you need extra PLLs enable them, but do not disable the ones that are enabled. )
CACRR same as CCSR

Here are settings for PLL I use

    ANADIG_PLL3_CTRL=ANADIG_PLL3_CTRL_ENABLE_MASK|ANADIG_PLL3_CTRL_POWER_MASK|ANADIG_PLL3_CTRL_EN_USB_CLKS_MASK;
    ANADIG_PLL5_CTRL=ANADIG_PLL5_CTRL_ENABLE_MASK|ANADIG_PLL5_CTRL_DIV_SELECT(1);
    ANADIG_PLL2_CTRL=ANADIG_PLL2_CTRL_ENABLE_MASK|ANADIG_PLL2_CTRL_DIV_SELECT(1);
    ANADIG_PLL1_CTRL=ANADIG_PLL1_CTRL_ENABLE_MASK|ANADIG_PLL1_CTRL_DIV_SELECT(1);
    ANADIG_PLL4_CTRL=ANADIG_PLL4_CTRL_ENABLE_MASK|ANADIG_PLL4_CTRL_DIV_SELECT(49);
    ANADIG_PFD_528_SYS=ANADIG_PFD_528_SYS_PFD4_FRAC(0x12)|ANADIG_PFD_528_SYS_PFD3_FRAC(0x18)|ANADIG_PFD_528_SYS_PFD2_FRAC(0x15)|ANADIG_PFD_528_SYS_PFD1_FRAC(0x13);

    ANADIG_PLL4_NUM = 0x04DD2F15;
    ANADIG_PLL4_DENOM = 0x1FFFFFDB;
5

Thank you,
I’m going to check carefully all of these settings.
When A5 loads a firmware and starts M4 core (Rpmsg library), at which speed does it configures core clock for M4?
And bus clock?

One more thing: when you set ANADIG_PFD_528_SYS register, do you mean ANADIG_PLL2_PFD (at address 0x40050100)?
I can’t find ANADIG_PFD_528_SYS in VFxx hardware reference manual.