SPI Clock level of SPI mode 3 failure

Technical Support
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1

The SPI clock in mode 3 does not work correct. Expected is clock polarity high and active edge positive. After each 8 bit, the SPI Clock is set to low again:
[upload|j3HIFfPc/5ccb7oy4EOC12X6SyE=]

We have an AD7793 connected to this SPI clock and have now troubles with the communication, because of this addition edges. (Because of historical reason, we can’t use CS.)
This is what our AD7793 expects:

[upload|GhZa4Q1qehhfwEI++NaapKeDffA=]

I have also checked the SPI clock of the PXA320 and it was exactly the SPI signal the AD7793 needs.
Because we run out of PXA320, we don’t have time to develop an new hardware and really need this bug fixed in the SpiLpi.lib for the iMX6. We need at least an additional spi mode for a spi clock, so it behaviors like the spi driver of PXA320.

2

Dear @rgu
It’s not really a bug - as long as the SPI chip select is active, all signals are correct, according to the SPI mode. This issue is documented in the library release notes.

However, I understand your problem. So far we didn’t have a customer who couldn’t easily work around the issue, therefore we prioritized other features.
I will bring up the topic on our weekly development meeting and inform you about the outcome. Do you have some information about the schedule - until when would you need a fix?

Regards, Andy