Reduce UART reference clock on VF50

Technical Support
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1

Hello,

I need to use an UART of the VF50 at 300 baud.
The reference clock used for the UART (module clock) seems to be set to 66 MHz.
In the Vybrid Reference Manual, chapter 49.4.3, there is this rule :
UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD))
SBR is a 13 bit register and BRFD is between 0 and 1.
In my case, the smallest speed that I obtain is 503 bit per sec.

On the next page in the Vybrid Reference Manual is the
“Table 49-232. Baud rates (example: module clock = 10.2 MHz)”.

Well, I need to change the value of the module clock !

Know somebody how to do it under linux ?

Kind regards

2

Hi Patrick

We are working on this question and will come back soon to you. By the way, which carrier board are you using? Are you using an toradex official image and did you create you own bsp? Can you give the link to the the Vbrid Reference Manual?

Thanks and best regards
Jaski

3

Hi Jaski,

We are using our own carrier board, the aartesys easy gateway. It’s a DIN rail device with one or two ethernet interface, a RS485 interface connected to the “UART B” (pin 32, 34, 36 and 38 of the VF50 module) and a Telit Cellular module connected to the USB interface.

Concerning the RS485 interface, our board is very similar to the Colibri evaluation board v. 3.2 : the same UART is connected to a RS485 transceiver, an Exar SP3072EEN-L in our case, and then it goes to the RS485 bus.

I have created my own BSP : I have configured and compiled the kernel sources from the toradex git (git://git.toradex.com/linux-toradex.git) to create my own kernel and root FS.
I still using the original toradex U-Boot binary.

The Vybrid reference manual can be found here :

I just see : this is “new” version of the document.
The references that I mentioned in my original question was based on the “Vybrid Reference Manual, Rev. 7, 06/2014, Freescale Semiconductor, Inc.”
In the new document, the “VFxxx Controller Reference Manual, Rev. 0, 10/2016, NXP Semiconductors”, the corresponding text is under the chapter 12.3.4.3 Baud rate generation, pages 2698 and 2699.

Kind regards,
Patrick

4

Hi Patrick

Can you try this patch for uboot?

--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -48,6 +48,8 @@ static u32 get_mcu_main_clk(void)
        sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
 
        ccm_cacrr = readl(&ccm->cacrr);
+       ccm_cacrr = ccm_cacrr | CCM_CACRR_IPG_CLK_DIV_MASK;
+       writel(ccm_cacrr, &ccm->cacrr);
        armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
        armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
        armclk_div += 1;
5

Hi Jaski,

It seems to work. the module clock is now 33 MHz instead of 66 MHz.

I will continue with the tests tomorrow.

Thanks and best regards,
Patrick

6

Hi Patrick, you are welcome.

7

Hi Jaski,

The solution with a modified U-boot with your patch is working well for my application and covers my needs.

Thanks for your help.

With kind regards,
Patrick

8

Perfect, that it works.