Imx7 GPIO value not setting as high

Technical Support
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1

Hi all,

I am using colibri imx7d 1gb version with colibri evaluation board.
I was just testing out the gpio.
I want to set SODIMM 102 as high.
So i did the following things. But value is not setting high at all.
I did try with other gpio, but value remain 0.

root@colibri-imx7-emmc:/sys/class/gpio# uname -a
Linux colibri-imx7-emmc 4.1.44-2.7.4+gb1555bf #1 SMP Wed Oct 4 21:39:05 UTC 2017 armv7l GNU/Linux
root@colibri-imx7-emmc:/sys/class/gpio# echo 145 > export 
root@colibri-imx7-emmc:/sys/class/gpio# ls
export       gpio145      gpio42       gpiochip0    gpiochip128  gpiochip160  gpiochip192  gpiochip32   gpiochip64   gpiochip96   unexport
root@colibri-imx7-emmc:/sys/class/gpio# cd gpio145
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# cat value 
0
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# cat direction 
in
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# echo "out" > direction 
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# cat direction 
out
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# echo 1 > value 
root@colibri-imx7-emmc:/sys/class/gpio/gpio145# cat value 
0
2

Did you make sure the pins in question are also muxed properly in the device tree as explained in the following article on our developer website?

3

My imx7-colibri.dtsi looks like this.

&iomuxc {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_3
&pinctrl_hog_4 &pinctrl_hog_5 &pinctrl_hog_6
&pinctrl_hog_7>;

imx7d-colibri {
	pinctrl_hog_1: hoggrp-1 {
		fsl,pins = <
			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 USBH OC */
   			/*	MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x74   SODIMM 55 */
		/*	MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x74  SODIMM 63 */
			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0X14 /* SODIMM 77 */
			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x14 /* SODIMM 95 */
			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11	0x14 /* SODIMM 99 */
			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
		>;
	};
4

Check also the description of the SION bit here and search the community for SION.

5

Pinmux looks good. It works for me:

root@colibri-imx7:/sys/class/gpio# echo 145 > export
root@colibri-imx7:/sys/class/gpio# cd gpio145
root@colibri-imx7:/sys/class/gpio/gpio145# cat value
0
root@colibri-imx7:/sys/class/gpio/gpio145# cat direction 
in
root@colibri-imx7:/sys/class/gpio/gpio145# echo "out" > direction 
root@colibri-imx7:/sys/class/gpio/gpio145# echo 1 > value
root@colibri-imx7:/sys/class/gpio/gpio145# cat direction 
out
root@colibri-imx7:/sys/class/gpio/gpio145# cat value 
1

Do you have other modifications in the device tree? What carrier board are you using? Are you sure the pin is not tied to GND?

6

Hi,
I am using colibri evaluation board rev 3.2. I have not made any modification other than enabling the ecspi2 and ecspi1.

7

Hi,
After setting SION bit its working, thankyou.

8

You are very welcome.