There is a camera with LVDS output connected to the THC63LVD1024 converter (720[link text][1]p30 video format). The chip is connected to CSI0, Y to D12 ~ D19, CbCr to D2 ~ D9, using DATA_EN, VSYNC, HSYNC, PIXCLOCK.
The device tree is configured as follows:
pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
fsl,pins = <
MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 PAD_CTRL_HYS_PD
MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 PAD_CTRL_HYS_PD
MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0xb0b1
MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0xb0b1
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0xb0b1
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0xb0b1
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0xb0b
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0xb0b1
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0xb0b1
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0xb0b1
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 PAD_CTRL_HYS_PD
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 PAD_CTRL_HYS_PD
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0xb0b1
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
>;
};
thc63lvd1024: thc63lvd1024@22 {
compatible = "thc63lvd1024";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
clocks = <&clks 200>;
clock-names = "csi_mclk";
csi_id = <0>;
mclk_source = <0>;
mclk = <74250000>;
status = "okay";
};
And also the kernel files (attached) are edited, the patch was taken as a basis. IPU_CSI0_SENS_CONF is configured as needed. I tried to set CSI0 to bt.1120 mode. But I never managed to capture the video with gstreamer.
What am I doing wrong?
[1]: https://share.toradex.com/2j1lt7odkgiqeza?direct
hi guffigubber
Welcome to the Toradex Community!!!
Could you provide the version of the hardware and software of your module? Which carrier Board are you using?
Which signals from the camera and the THC63LVD1024 converter are connected to the apalis imx6 module?
Thanks!
We use a motherboard of our own design.
THC63LVD1024 is connected using the circuit recommended by the camera manufacturer (attached).
The outputs from the microcircuit are connected to the processor in accordance with Table 5-63 Camera Interface Colour Pin Mapping (Apalis iMX6 Datasheet Doc.Rev.1.3) YCbCr 16bit 1 cycle, where Y[0] - Y[7] correspond to DATA12 - DATA19; C[0] - C[7] correspond to DATA02 - DATA09; DATA0, 1, 10, 11 - 0 and use DATA_EN, VSYNC, HSYNC, PIXCLOCK.
OK, I managed to get an image using the camera!
It was necessary to turn off MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN to PAD_CTRL_HYS_PD .
But now I have such an image (1080p30, V4L2_PIX_FMT_YUYV, IPU_CSI_DATA_WIDTH_8, IPU_CSI_CLK_MODE_GATED_CLK)
Perfect, that is working.
But now I have such an image (1080p30, V4L2_PIX_FMT_YUYV, IPU_CSI_DATA_WIDTH_8, IPU_CSI_CLK_MODE_GATED_CLK).
Could you upload the image again? What exactly is not working?
Moreover, these rectangles with the image each time are displayed differently at the start gstreamer
and feel frame rate lower than 30 fps
hi,
unfortunately your image was not uploaded. Could you try to upload it again and also explain what is the issue?
Thanks.
uploaded a photo to google disk, here is link
the image does not have enough colors.
the image itself consists of 4 pictures and they change their location each and timefeel frame rate lower than 30 fps
UPD: Set 10 bits per color, got the following result (link picture)
Now I see one frame, but it’s also not displayed as a whole. And now the image is green
how are you capturing the image? Can you share the gstreamer commands you are using?
I’m using udp, because there is no output to the monitor on our motherboard
gst-launch-1.0 imxv4l2videosrc device=“/dev/video0” ! rtpvrawpay ! udpsink host=192.168.5.163 port=5554 -e -v
Hi
Thanks for the the commands.
After the discussion regarding your last not complete picture in green with the hardware engineer, the doubt is on wrong wired sync and other signals. Therefore could you please send us the datasheet of the camera, the complete camera to chip to Ixora schematic in pdf format, please?
Additionally could you make a picture of this test picture?
Thanks and best regards
first image is 8 bits per color;
second picture is 10 bits per color
we use Sony EV7520, it is connected to a chip THC63LVD1024, according to the scheme recommended by the manufacturer (page 64 datasheet camera) link to a separate page. Connection to a processor module looks like this
Thanks for the help!
hi
You are welcome. Thanks for the Information. We will look into it and come back soon to you.
I have spent quite some time on the datasheet of the Sony camera. Maybe I found the reason for the strange behavior. The LVDS interface of the camera can be set into single or double mode. In the double mode, every other pixel is transported over the secondary LVDS channel. But this is not the only thing that is changing in this mode. Also the mapping of the pins are changing. In the single mode, the DE signal is mapped to pin 103 of the Thine receiver while in the double mode, the signal is mapped to pin 83 (see pages 61 and 63 of the Sony datasheet).
In the BT.1120 standard, the DE pin is used for the synchronization. If that signal is missing, it will not be possible to synchronize the stream. When I look at your images, it looks like the image is not only having issues to synchronize, there are actually multiple smaller pictures. If the the camera is set to the double mode, but you have set the Thine into the single mode, it would actually result in a data stream in which only the even pixels are send to the i.MX6. This means the pixel clock is half of the original and the picture would be half the size. A third evidence of my theory is the fact that we only have a green image. In the BT.1120, the color bits are altered (if color mode 4:2:2 is used) between the even and the odd bits. This means, on the even bits one color component is transported, while on the odd the other. By having only the even bits, we are loosing one color component.
Therefore, is suspect that the camera is set to dual LVDS mode while the Thine transceiver is running in the single LVDS mode. Can you check the settings of the camera? In which mode is it? Can you check your schematics. Which one of the example schematics did you implement, is it the one on page 64 or 62? Have you set all the mode pins of the Thine correctly? Have you attached the pins correctly? Can you send me your actual schematics in order to check that?
It would be also interesting to measure the DE signal that goes to the module. Do you see the correct timings when you measure that signal with a scope?
Hi
Camera LVDS Mode set to Double output, we have implemented a scheme from the page 64 (LVDS receiver circuit example 3 (Double output)).
Thine scheme, mode set MODE<1:0> = LH - Dual Link (Dual-in/Single-out).
Once again looked at the motherboard project, the outputs from the microcircuit are connected to the processor in accordance with Table 5-63 Camera Interface Colour Pin Mapping (Apalis iMX6 Datasheet Doc.Rev.1.3) YCbCr 16bit 1 cycle, where Y[0] - Y[7] correspond to DATA12 - DATA19; C[0] - C[7] correspond to DATA02 - DATA09; DATA0, 1, 10, 11 set 0 and use DATA_EN, VSYNC, HSYNC, PIXCLOCK.
Thank you for the schematics. I reviewed it and did not find any issue. The connections seem all to make sense and the modes are set correctly. The next thing we should check is whether the signals are de-serialized correctly. It is very important to have the signal lengths of the LVDS pairs matched precisely. A length difference between the clock pair and data pairs can lead to shift the output signals.
If the camera outputs the synchronization signals, the best way to check whether everything is correct is to measure the de-serialized sync signals. Can you please measure the HSYNC, VSNC, and DE signals with a scope? You can measure them directly at the series resistors (R66, R71, and R54). Check whether the signals are clean. Make sure that there are no spikes and the signals have the expected frequency and form.
Unfortunately, the official BT.1120 format does not really use the synchronization signals (HSYNC, VSYNC, DE), since the synchronization is embedded in the data stream. Therefore, there is a chance that the Sony camera does not output the sync signals. However, it is worth checking them. If there are present, we know at least that the de-serialization works flawless.
Well, we’ll see and answer later.
yes, 1120 does not officially have any signals. I think that the processor in the gated mode should work with synchronization signals. but not as 1120, but as ycbcr
Well, we’ll see and answer later.
yes, 1120 does not officially have any signals. I think that the processor in the gated mode should work with synchronization signals. but not as 1120, but as ycbcr
Thanks. We will wait for your update.
Hi, sorry for the long answer.
I attach pictures from an oscilloscope with signatures
IMG1 IMG2 IMG3
