I try to set up a dual display system with a display on both lvds channels, but I can’t get the desired frequency on my LVDS output.
fbset shows the correct frequnecy of 71.1 MHz, but the measured frequency is just 37.7MHz.
i think it might be the parent clock, because i get error message during start up and the lvds clock is obviously not on PLL5 as you can see below.
Do you have any idea why the clock isn’t 71 MHz ?
Thank you and best regards
mode "1280x800-60"
# D: 71.104 MHz, H: 49.377 kHz, V: 59.997 Hz
geometry 1280 800 1280 800 32
timings 14064 0 150 0 13 10 10
accel false
rgba 8/16,8/8,8/0,8/24
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 1 1 528000000 0 0
periph2 1 1 528000000 0 0
mmdc_ch1_axi_podf 1 1 264000000 0 0
mmdc_ch1_axi 2 2 264000000 0 0
ldb_di0_sel 1 1 264000000 0 0
ldb_di0_div_7 0 0 37714285 0 0
ldb_di0_div_sel 0 0 37714285 0 0
ldb_di0_div_3_5 1 1 75428571 0 0
ldb_di0_podf 1 1 37714286 0 0
ldb_di0 1 1 37714286 0 0
ipu2_di1_sel 1 1 37714286 0 0
ipu2_di1 1 1 37714286 0 0
ipu2_pclk1_sel 1 1 37714286 0 0
ipu2_pclk1_div 1 1 37714286 0 0
ipu2_pclk1 1 1 37714286 0 0
[ 0.000000] ccm: invalid ldb_di0 parent clock: 174
[ 0.000000] ccm: invalid ldb_di1 parent clock: 174
[ 0.000000] clk: failed to reparent ldb_di0_sel to pll5_video: -38
[ 0.000000] clk: failed to reparent ldb_di1_sel to pll5_video: -38
[ 0.000000] clk: failed to reparent ldb_di0_sel to pll5_video: -38
[ 0.000000] clk: failed to reparent ldb_di1_sel to pll5_video: -38
And the device tree settings:
&ldb {
status = "okay";
// split-mode;
// dual-mode;
lvds-channel@0 {
//fsl,data-mapping = "spwg"; /* "jeida";*/
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing_xga_ol>;
timing_xga_ol: 1280x800 {
clock-frequency = <71100000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <0>;
hfront-porch = <150>;
vback-porch = <0>;
vfront-porch = <13>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
lvds-channel@1 {
//fsl,data-mapping = "spwg"; /* "jeida";*/
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing_xga_di>;
timing_xga_di: 1280x800 {
clock-frequency = <71100000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <0>;
hfront-porch = <150>;
vback-porch = <0>;
vfront-porch = <13>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
};
