Colibri iMX6ull ksz8863 switch on the carrier support

Technical Support
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1

instead of using the ethernet switch on the colibri iMX6ull board, we would like to use the ksz8863 on the carrier board. The ksz8863 is connecting to the colibri using rmii. please refer to the following attached image for detailed pin connections for the switch.

We will use pin 8 as the clock input, from ksz to board at 50 MHz.

I am not sure how do I modify the device tree/kernel to make that work. If you can provide me the detailed instructions, that would be very appreciated.

thank you

Weixiong

2

We haven’t tried a ksz8863 switch before so we don’t have a ready to use solution. You can take a look to this threads:

3

we are using pin 8 as the input clock (switch to imx6 board). Do I set the ALT mode to ALT3 by using MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1? It is not clear to me this is for input or output clock. If anyone know the answer, please let me know.

4

From Colibri iMX6Ull datasheet:

  • anatop.ENET_REF_CLK1 - 50MHz Reference clock that is provided from the MAC to the PHY or from the PHY to the MAC*

Direction is set by bit 17 (ENET1_TX_CLK_DIR) of IOMUXC_GPR_GPR1 register.

5

thank you for the response. How do I set IOMUXC_GPR_GPR1?

6

It’s a driver responsibility.

For example, here we inform a fec driver that stop-mode controlled by bit 4 at &GPR + offset 0x10 . Which is IOMUXC_GPR_GPR4

Exactly field you should put to DT depends on driver you are using for your ksz8863 switch.

7

the driver we will be using is the KSZ886X, it is actually in the same file as the KSZ8041, which is on the iMX6ull board.
drivers/net/phy/micrel.c

I am looking at the driver code, and still do not know how to set the ENET1_TX_CLK_DIR bit on register IOMUXC_GPR_GPR1, and do not know if I should set it to 0 or 1 for input clock.

8

The KSZ8041 on Colibri board uses 50 MHz ref clock as an input.
Both ref clocks (ENET_REF_CLK1 and ENET_REF_CLK2) are enabled and set as a iMX output by default here.

So if your ksz8863 require this clock as an input as well it’s already enabled. You just need to do a proper pin muxing to get on pin 8 (MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1). Check for details here.

9

yes, I have been trying to do exactly that.

our ksz8863 has been configured to output the 50MHz clock. The direction of the clock is from PHY (ksz8863) to the MAC (board), by using pin 8.

for pin 8, we configure it to be:
MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x4001b031
However, it does not work.
I went through the bit definitions in here, however, I don’t find any of them specifying the pin to be input or output. Should I hardcoded it in the mach-imx6ul.c?

also, for
#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0
do I need to change the last 0 (input _val) to 1?

10

The direction of the clock is from ksz8863 to the board, by using pin 8.

I’m not sure if driver you are going to use support this mode. The KSZ8041 on Colibri module configured backward.

However, it does not work.

What exactly doesn’t work? Ethernet driver?

I don’t find any of them specifying the pin to be input or output

Device Tree pin muxing doesn’t specify direction

do I need to change the last 0 (input _val) to 1?

No, if you going to use ALT3 mode for this pin:

IOMUXC_ENET1_REF_CLK1_SELECT_INPUT field descriptions
Field Description
31–2 This field is reserved.

DAISY Selecting Pads Involved in Daisy Chain.
Instance: enet1, In Pin: rmii
00 GPIO1_IO00_ALT3 — Selecting Pad: GPIO1_IO00 for Mode: ALT3
01 GPIO1_IO04_ALT0 — Selecting Pad: GPIO1_IO04 for Mode: ALT0
10 ENET1_TX_CLK_ALT4 — Selecting Pad: ENET1_TX_CLK for Mode: ALT4
11

thank you alex.tx for the help. It works now.
After hardcoding the clock direction bit in mach-imx6ul.c, Linux was able to detect the switch and it worked. However, it does not work for one of the physical ports, which require some modifications from the the device_phy.c, but that is a different issue.

12

Thank you for the update.