How to enable second SDIO interface on Colibri iMX6

I have connected a WF111 WiFi module to the second SDIO interface of my Colibri iMX6S.

PINS:
174 - SD_2_CD
093 - SD_2_CLK
069 - SD_2_CMD
098 - SD_2_DATA0
106 - SD_2_DATA1
130 - SD_2_DATA2
099 - SD_2_DATA3

Which modifications to my kernel / device tree are required to enable this interface and disable the primary functions?
Is there any documentation available regarding this procedure?

Hi

actually you have two questions:

How to enable a second SDIO interface:

You would have to make sure the pinmuxing is right for those pins and you would have to configure the second instance of the usdhc driver.
Have a look at the device-tree modification article.
For the usdhc node compare with the existing node for SD1.
After you deployed the device-tree to the module you should be able to use SD cards on that interface. So if you actually have an SD slot you can test the first step towards your SDIO interface.

How to get a WF111 WiFi module up and running:

Whatever that ‘WF111’ is, you need to find what driver is able to work with it.
If there is a driver in our kernel tree enable it in the kernel configuration. If not you may need to get the sources for the kernel and compile it against our kernel tree.

Maybe the card needs firmware which you likely need to deploy in /lib/firmware/, usually once you have the driver loading at boot but the firmware is not deployed you get a kernel log saying so stating the firmware filename.

Max

Hi Max,

thanks for your answer and sorry for my bit unspecific question.

The WF111 is a WiFi Module from Bluegiga (now Silicon Labs). I already had compiled the driver against the colibri kernel and it worked at SD1 interface of the Colibri Evaluation Board.

So the missing part, was the modification of the device tree to enable the second SD interface. In the meantime I created a new dts file for my custom carrier board based in “imx6dl-colibri-eval-v3.dts”.
The relevant parts to enable usdhc2 are:

...
&iomuxc {
    usdhc {
        pinctrl_mmc2_cd: gpio_mmc2_cd {
            fsl,pins = <
                MX6QDL_PAD_GPIO_4__SD2_CD_B    PAD_CTRL_NO  /* MMC2 CD */
            >;
        };
        pinctrl_usdhc2: usdhc2grp {
            fsl,pins = <
                MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
                MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
                MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
                MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
                MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
            >;
        };
    };
};
...
/* overwrite pinctrl_* nodes without the pins used for SD2... */
&iomuxc {
    csi {
        /* CSI pins used as GPIO */
        pinctrl_csi_gpio_1: csi_gpio-1 {
            fsl,pins = <
                MX6QDL_PAD_EIM_A24__GPIO5_IO04   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_D18__GPIO3_IO18   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_A19__GPIO2_IO19   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_D29__GPIO3_IO29   PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_A23__GPIO6_IO06   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_A20__GPIO2_IO18   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_A17__GPIO2_IO21   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_A18__GPIO2_IO20   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_EB3__GPIO2_IO31   PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_D17__GPIO3_IO17   PAD_CTRL_HYS_PU
            >;
        };
    };
    weim {
        /* DATA[16:31]  used as GPIO */
        pinctrl_weim_gpio_3: weim_gpio-3 {
            fsl,pins = <
                MX6QDL_PAD_EIM_LBA__GPIO2_IO27     PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_BCLK__GPIO6_IO31    PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_CS3__GPIO6_IO16   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_CS1__GPIO6_IO14   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_RB0__GPIO6_IO10   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_ALE__GPIO6_IO08   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09  PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_CS0__GPIO6_IO11   PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_CLE__GPIO6_IO07   PAD_CTRL_HYS_PU
                MX6QDL_PAD_GPIO_19__GPIO4_IO05     PAD_CTRL_HYS_PU
                MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19   PAD_CTRL_HYS_PU
                MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 PAD_CTRL_HYS_PU
                MX6QDL_PAD_GPIO_5__GPIO1_IO05      PAD_CTRL_HYS_PU
                MX6QDL_PAD_GPIO_2__GPIO1_IO02      PAD_CTRL_HYS_PU
            >;
        };
        /* DQM[0:3]  used as GPIO */
        pinctrl_weim_gpio_4: weim_gpio-4 {
            fsl,pins = <
                MX6QDL_PAD_EIM_EB0__GPIO2_IO28  PAD_CTRL_HYS_PU
                MX6QDL_PAD_EIM_EB1__GPIO2_IO29  PAD_CTRL_HYS_PU
                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 PAD_CTRL_HYS_PU
            >;
        };
    };
};
...
&usdhc2 {
    label = "MMC2";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_mmc2_cd>;
    cd-gpios = <&gpio1 4 0>;
    vmmc-supply = <&reg_3p3v>;
    bus-width = <4>;
    no-1-8-v;
    status = "okay";
};
...
/ {
...
    aliases {
...
        mmc2 = &usdhc2; /* MMC 4bit - used for SDIO wifi module */
    };
...

With those modifications my WiFi module is working at usdhc2.

Any suggestions or improvements welcome.

hi,

I am using WF111 having SDIO interface (usdhc1) with the imx6solosabresd custom board,the unifi driver is not showing up any message of card detection.
Could you share how the unifi driver is specified in the device tree?
Please share the files with the required changes made .