Colibri-T20 SPI2

Hello!

I am trying to use multiple SPIs on Colibri T20 under Linux (Toradex OpenEmbedded Angstrom) on a custom carrier board.

I see all of them as spidev (spidev0.0, spidev.1.0, spidev1.1, spidev1.1, spidev1.2, spidev1.3, spidev2.0, spidev2.1, spidev2.2. spidev2.3).

spidev3 is used for dual CAN bus interfacing – this works
All spidev0 and spidev2 are also working.

But despite pin multiplexing has been configured for SPI2 on corresponding pins there is no communication on spidev1.

I am aware that SPI2 pins are multiplexed with LCD_D19-D21 but pin-muxes are set and LCD_Dxx signals are tri-stated.

Would you please advise.

Thanks!

Can you provide the diff of the kernel source tree changes?

Thanks for your quick response!
Please take a look at the file attached (ioc.patch).
link text

I think the problem is probably because of the following lines:

//multiplexed SPI2_CS0_N, SPI2_MISO, SPI2_MOSI and SPI2_SCK
+#if 0
{TEGRA_GPIO_PM2, GPIOF_IN, “SODIMM pin 136”},
{TEGRA_GPIO_PM3, GPIOF_IN, “SODIMM pin 138”},
{TEGRA_GPIO_PM4, GPIOF_IN, “SODIMM pin 140”},
{TEGRA_GPIO_PM5, GPIOF_IN, “SODIMM pin 142”},

+#endif

It should become #if 1 in order for those pins to become tri-stated and not mess with SPI2 pads which are on Colibri-T20 shared with LCD_D18/19/20.

Going to try it out.
What do you think?

Thanks!

Well, still no success! Not even a clue. I think kernel patching has been done by the book but no result. I’ve got all spidev devices available. SPI1 and SPI3 are working OK. SPI4 is used for dual CAN bus. Just SPI2 is not working when trying to communicate.
I know SPI2 pins are shared with LCD pins. Because of that LCD pins M2, M3, M4, M5 have been tri-stated, and indeed they are show as such in /sys/kernel/debug/gpio.

Any ideas would be highly appreciated.

Thanks!

I quickly looked at your patch concentrating on the SPI2 pinmux only. You seem to use SPI2 pinmux on SPIA, SPIB and SPIC but then you also go on to pinmux SPID for SPI2 again. There are now two pinmux instances for SPI2 or to be more specific for SPI2_MOSI which is a pinmux conflict and cannot be resolved. Assuming your intention was to have multiple chip selects, you can for example select SPIA, SPIB and SPIC which would give SPI2_MOSI, SPI2_MISO and SPI2_CS0_N and SPI2_SCK respectively. SPIG and SPIH can be selected to provide additional chip selects.

	/* X0, X1, X2, X3, X4, X5, X6 and X7 */
	{TEGRA_PINGROUP_SPIA,	TEGRA_MUX_SPI2,		TEGRA_PUPD_NORMAL,	TEGRA_TRI_NORMAL},
	{TEGRA_PINGROUP_SPIB,	TEGRA_MUX_SPI2,		TEGRA_PUPD_NORMAL,	TEGRA_TRI_NORMAL},
//alternate SPI3_CS1_N
	{TEGRA_PINGROUP_SPIC,	TEGRA_MUX_SPI2,		TEGRA_PUPD_PULL_UP,	TEGRA_TRI_NORMAL},
	{TEGRA_PINGROUP_SPID,	TEGRA_MUX_SPI2,		TEGRA_PUPD_PULL_UP,	TEGRA_TRI_NORMAL},
//required for SPI2_CS1_N on SODIMM pin 102
	{TEGRA_PINGROUP_SPIE,	TEGRA_MUX_SPI2_ALT,		TEGRA_PUPD_PULL_UP,	TEGRA_TRI_NORMAL},
	{TEGRA_PINGROUP_SPIF,	TEGRA_MUX_RSVD,		TEGRA_PUPD_NORMAL,	TEGRA_TRI_NORMAL},

	/* USBH_PEN */
	{TEGRA_PINGROUP_SPIG,	TEGRA_MUX_SPI2_ALT,	TEGRA_PUPD_PULL_UP,	TEGRA_TRI_NORMAL},
	/* USBH_OC */
//alternate SPI3_CS0_N
	{TEGRA_PINGROUP_SPIH,	TEGRA_MUX_SPI2_ALT,	TEGRA_PUPD_PULL_UP,	TEGRA_TRI_NORMAL},

You’re right. We do need multiple Chip Select signals for SPI2. That’s why SPIH, SPIG, and SPIE have bee muxed as TEGRA_MUX_SPI2_ALT.

But indeed SPID is wrong.

It was an old patch to an older kernel version. But the patch was relevant to the old kernel and things have changed quite a bit since then. Applying the same patch to the newer kernel was not straightforward and thus error prone.

I will change accordingly and try it out reporting the outcome in a timely fashion.

Thanks!